1. Field
The present disclosure relates to power controllers, more particularly to solid state power controllers.
2. Description of Related Art
Traditionally, solid state power controller (SSPC) designs have used floating channel controls referenced to a load line with communications isolators and isolated floating power supplies for each and every channel. This has served its intended purpose even though it has resulted in significant parts count and board space as well as some contribution to power dissipation on the board.
Alternate approaches have used a common positive reference supply for voltage distribution (e.g., 28V) or have used ground as a reference, but have continued to use N-channel field effect transistor (FET) (e.g., MOSFETs) requiring level translation to drive the gate along with an additional gate voltage power supply. Such approaches reduce the isolation components on the communications interface and reduced the number of isolated power supplies but also add level translation, power isolation, and communication isolation circuits for each and every N-channel FET and/or FET group. Also if ground is used as a reference, then level translation for current sensing is also required.
Such conventional methods and systems have generally been considered satisfactory for their intended purpose. However, there is still a need in the art for improved solid state power controllers. The present disclosure provides a solution for this need.